IEEE Design & Test September/October 2002 Features Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era Jaume Segura and Peter Maxwell IDDQ Test: Will It Survive the DSM Challenge? Sagar S. Sabade and D.M.H. Walker Resistance Characterization for Weak Open Defects Rosa Rodr­guez Montaá©s, Paul Volf, and Jos© Pineda de Gyvez Noise Generation and Coupling Mechanisms in Deep-Submicron ICs Xavier Aragon¨s, Jose Luis Gonz¡lez, Francesc Moll, and Antonio Rubio Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, Kaushik Roy, Charles F. Hawkins, W. Robert Daasch, and Manoj Sachdev High Defect Coverage with Low-Power Test Sequences in a BIST Environment Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, and Hans-Joachim Wunderlich Special ITC Section Guest Editors' Introduction: Stressing the Fundamentals Robert C. Aitken and Donald L. Wheater Efficient Sequential Test Generation Based on Logic Simulation Shuo Sheng and Michael S. Hsiao Extending OPMISR Beyond 10x Scan Test Efficiency Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion Keller, David Scott, Bernd Koenemann, and Takeshi Onodera Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort W. Robert Daasch, James McNames, Robert Madge, and Kevin Cota Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers Sule Ozev, Christian V. Olgaard, and Alex Orailoglu Special Feature Virtual Simulation of Distributed IP-Based Designs Marcello Dalpasso, Alessandro Bogliolo, and Luca Benini Departments EIC Message Roundtable Conference Reports TTTC Newsletter DATC Newsletter Panel Summaries --------------------------------------------------- If you wish to be removed from this mailing list, send a message to listserv@computer.org with the following text in the body of the message: unsubscribe dt_subscribers ---------------------------------------------------